Tera Introduces Teraform® RTL Design Consultant to Improve Quality of HDL Code and Streamline RTL Handoff

CAMPBELL, Calif.-JUNE 11, 2002-Tera Systems, Inc. today introduced TeraForm®-RTL Design Consultant (TeraForm®-RDC), a new class of design analysis software that significantly improves the quality of register-transfer level (RTL) code prior to design implementation. Using the new tool, system-on-chip (SoC) designers and ASIC vendors can detect and correct errors early in the design process, thereby shortening the overall design cycle and streamlining the RTL handoff step for design implementation.

"If you've got timing or congestion problems in implementation, it's likely that they started with the RTL and that they were made worse in synthesis." says Dan Deisz, senior director LSI Logic design services. "TeraForm-RDC is the tool we're using to check our customer's RTL. We check against our specific rules for physical realization and timing thereby creating a stable, predictable turnaround time for ASIC implementation. "

Engineering expertise and experience in deep submicron physical design is at a premium and in short supply today. Growth in complexity of designs requires that designers possess cross-domain expertise-system engineers (formerly focused on high level language based design) need to learn the art of chip layout and physical implementation specialists need to learn the subtleties and coding style implications of RTL.

TeraForm-RDC directly addresses the need for this cross-domain knowledge by encapsulating the knowledge of both expert RTL-designers and physical implementation specialists in a reusable form. TeraForm-RDC's unique physical modeling at the RT level allows system engineers to interactively explore and debug their entire design, not just individual RTL blocks. The tool can check the RTL for semantics, timing, area, congestion, synthesis constraints, and layout implementation-related issues prior to passing the design to the next implementation step. At each step of the design flow, the tool not only reduces future iteration steps, but also provides invaluable RTL links to the cause of the error, greatly accelerating design debug.

"There has been a breakdown in communication between design implementation teams and front-end SoC designers as complexity continues to grow with deep submicron semiconductor technologies," said Mark Miller, vice president of marketing and business development at Tera Systems. "Our new RTL Design Consultant product gives both ASIC vendors and system designers the ability to automate RTL analysis that pinpoints errors early in the design flow and enables them to quantify the quality of their RTL based on their own established criteria. By encapsulating experiential design knowledge and best practices, TeraForm-RDC is becoming the next logical extension in the design flow resulting in a completed chip in less time."

TeraForm-RDC returns predictability to the design flow. It provides the missing communications channel at every level of design handoff, ensuring that block level designs integrate into the chip, that the chip level design is acceptable for layout and that the final design passes vendor specific handoff criteria. At each stage, it reduces iterations and allows problems to be corrected early at the RT level.

TeraForm-RDC provides a host of features and capabilities to allow users to perform expert analysis with minimal effort. The tool supports flexible, scalable rule sets and enables fast, easy development of new rules. Users can configure the GUI and format presentation of results for tabular or graphical display. They can also create rule sets to check for proprietary or vendor-specific errors and coding violations. In addition, TeraForm-RDC allows protection of these vendor-specific rule sets and their underlying intellectual property through compilation. TeraForm-RDC is tightly integrated with TeraForm®-VP (TeraForm-Virtual Prototype) for design visualization, cross probing and RTL debugging.

Teraform-RDC can check a large range of RTL coding, chip-level integration, synthesis, and layout issues. The tool will be released with a compliment of checks including identification of snaking timing paths, incomplete timing constraints and congestion detection at the RT level. For a complete list of supported functions, please contact Tera Systems directly at www.terasystems.com or visit us at the Tera Systems DAC booth 2032.

Pricing and Availability
Tera will offer both ASIC vendor-specific and generic versions of RTL Design Consultant as an option to TeraForm-VP. The ASIC vendor version will accept vendor-supplied rule sets to check structural and design implementation issues. The generic version will include an optimized and scalable TeraGate™ library with a diverse starter set of general semantic, structural and implementation rules. Both versions will be available in Q3 2002. Pricing starts at $25,000 US list.

About Tera Systems
Tera Systems, Inc. is the leader in Hardware Description Language (HDL)-based design planning technology for use by designers of complex System-on-Chip (SoC) semiconductors. The company's products provide early visibility into design quality, performance and manufacturability issues with the goal of preventing downstream problems with synthesis and physical design processes. Using the Tera Systems tools, SoC designers can ensure timing convergence and superior performance before reaching back-end layout or actual silicon where the costs of design errors or changes are extraordinarily high. Tera Systems partners with leading semiconductor vendors to develop highly predictable design methodologies and "golden" tool flows that dramatically accelerate the SoC design cycle. For more information, visit our web site at www.terasystems.com.

For more information contact:
Heather Sullivan
Tera Systems, Inc.
(408) 369-4528
heather@terasystems.com

Karen E. Tyrrell
VitalCom Marketing & PR
(650) 637-8212 x204
karen@vitalcompr.com